It is not difficult to verify if a clock input is terminated or not.
Normally the hw specs state that. When there is not a switch or sw setting, it is usually terminated.
You can use T connectors to chain clock inputs only when all inputs but the last one are not terminated, only the last input in the extreme must be terminated. The line must always be a bus, it must not have any branches, the t connectors can only be placed directly on the inputs without any extra cable branch.
If inputs are terminted, you must not use T connectors, but chain from each output to next input.
If termination is not correct, jitter can be much higher, caused by reflections in the wire. And the longer the wire, the larger the jitter.
Watching the clock signal in an oscilloscope can definitelly tell if the line is properly terminated or not. Also most often an ohm meter can also be used to check if an input is terminated. The ohm meter method is not 100% safe, (will fail if the input has a DC decoupling capacitor before the termination resistor), but works in most cases. Another reliable method is to place a 75 ohm resistor in series with the input: if the input is terminated the AC voltage in the input will be 1/2 of that before the series resistor, and nearly identical if the input is not terminated.
Also, TosLink, TDIF, SPDIF, AES-EBU, etc, have embedded clock. You can always lock to them instead of using a dedicated wordclock input. In the case of optical connections this is usually preferable.
post edited by jcatena - 2010/07/28 02:52:57